"<pre>
MODULE P300402

TITLE 'P3004A02'

"Firmware for Transmitter with Logic Chip (A3004)

"Copyright (C) 2005 Kevan Hashemi, hashemi@brandeis.edu, Open 
"Source "Instruments Inc.

"This program is free software; you can redistribute it and/or
"modify it under the terms of the GNU General Public License
"as published by the Free Software Foundation; either version 2
"of the License, or (at your option) any later version.

"This program is distributed in the hope that it will be useful,
"but WITHOUT ANY WARRANTY; without even the implied warranty of
"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
"GNU General Public License for more details.

"You should have received a copy of the GNU General Public License
"along with this program; if not, write to the Free Software
"Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
"02111-1307, USA.

declarations

"Inputs and Outputs"
CK   pin 38; "Clock From 32-kHz Oscillator"
SCK pin 43; "Slow Clock, or Global CLK0, Connected to Pin 44"
SCKO pin 44; "Source of SCK"
FCK pin 18; "Fast Clock, or Global CLK1 Connected to Pin 17"
FCKO pin 17; "Source of CK1"
TCK pin 19; "Transmission Clock, or Global CLK2 Connected to Pin 20"
TCKO pin 20; "Source of CK2"
CK3 pin 42; "Global CLK3 Connected to Pin 41"
CK3O pin 41; "Source of CK3"
TUNE pin 45 istype 'com'; "Tune Control for Transmitter"
!SHDN pin 34 istype 'com'; "Shutdown Control for Transmitter"
SRIN pin 21; "Serial Input from P2"
SRCK pin 22; "Serial Clock from P2"
TP1..TP3 pin 23,24,26 istype 'com'; "Test Points on P2"

"Nodes"
T0..T20 node istype 'reg'; "Timer Running off 32-kHz"
R1..R5 node istype 'com,keep'; "Ring Oscillator"
D0..D2 node istype 'reg'; "Ring Oscillator Divider"
TXS0..TXS4 node istype 'reg,pos'; "Transmitter State"
ACTIVE node istype 'reg'; "Active period of 32-kHz"
TXD node istype 'com'; "Transmitter Done"

"Sets"
full_time = [T20..T0]; "Chronometer Timer"
cycle_time = [T5..T0]; "Transmit Cycle Timer"
divider = [D2..D0]; "Ring Oscillator Divider"
txs = [TXS4..TXS0]; "Transmitter State"

equations

"We set SCK, one of the global clock pins, equal to"
"the 32-kHz input via the SCKOT pin."
SCKO=CK;

"The full timer runs off the 32-kHz clock"
full_time.clk=SCK;
full_time:=full_time+1;

"Active is true when the cycle time is zero"
ACTIVE.clk=!SCK;
ACTIVE:=(cycle_time==0);

"TXD is true when the transmitter is done transmitting"
TXD=(txs==31);

"The ring oscillator turns on when ACTIVE is asserted."
"Each gate in the ring adds 2 ns to the delay around"
"the ring, and there fore 2 ns to each half-period of"
"the ring oscillator. The period of the oscillation is"
"therefore 4 ns multiplied by the number of gates. We"
"have five gates, so the period is close to 20 ns, which"
"is a frequency of 50 MHz."
[R5..R1]=[R4..R1,!R5 & ACTIVE & !TXD];

"We use R5 to drive the FCK global clock pin through"
"FCKO at 50 MHz."
FCKO=R5;

"The divider creates 6 MHz by dividing the 50-MHz FCK"
"by eight."
divider.clk=FCK;
divider.aclr=!ACTIVE;
divider:=divider+1;

"We use D2 to drive the TCK global clock pin through"
"TCKO at 6 MHz and 32 kHz."
TCKO=D2;

"The transmitter state machine steps through all its"
"states when ACTIVE is asserted, and then stops in its"
"final state, waiting for !ACTIVE, which will reset it"
"to zero."
txs.clk=TCK;
txs.aclr=!ACTIVE;
when (txs==31) then txs:=31
else txs:=txs+1;

TUNE=( ((txs>=5) & (txs<=8))
  # ((txs==10) & T20)
  # ((txs==11) & T19)
  # ((txs==12) & T18)
  # ((txs==13) & T17)
  # ((txs==14) & T16) 
  # ((txs==15) & T15) 
  # ((txs==16) & T14) 
  # ((txs==17) & T13)
  # ((txs==18) & T12)
  # ((txs==19) & T11)
  # ((txs==20) & T10)
  # ((txs==21) & T9)
  # ((txs==22) & T8)
  # ((txs==23) & T7)
  # ((txs==24) & T6)
  # ((txs==25) & T5) 
  # ((txs==26) & T4)
  # ((txs==27) & T3)
  # ((txs==28) & T2) 
  # ((txs==29) & T1)
  # ((txs==30) & T0) );

SHDN=(txs==0)#(txs==31);

TP1=SHDN;
TP2=TUNE;
TP3=ACTIVE;

END