"<pre>
module P3007B

title 'P3007B'

"Verion 7, Last modified 02-MAY-06"

"This code eliminates any fancy division of a fast"
"clock to obtain the 40 MHz data clock, and instead"
"uses the Michael Bradshaw-style multi-stage ring"
"oscillator to produce a period of 25 ns directly."

declarations
  min_startup_edges=5;
  num_message_bits=24;
  max_transmission_time=250; "25-ns periods of DCK"
  fake_data=0;
equations

"Pins"
declarations
A pin 3; "LVDS input"
B pin 10 istype 'com'; "LVDS output"
C pin 43; "Comparator Output"
LB pin 8 istype 'com'; "Loop Back"
!RESET pin 22;"RESET"			
ARCK pin 20; "Asynchronous 32 kHz reference clock input"
DCK pin 39; "Data Clock on Global CLK2"
DCKO pin 42 istype 'com'; "Source of DCK"
!RW pin 59 istype 'com'; "RAM Write"
!RCE pin 66 istype 'reg'; "RAM Chip Enable"
!ROE pin 6 istype 'com'; "RAM Output Enable"
RA18..RA0 pin 85,80,79,78,16,17,19,31,30,53,
  54,55,56,58,67,69,70,71,72 istype 'com'; "RAM Address"
ram_addr = [RA18..RA0];
RD7..RD0 pin 9,11,14,15,60,61,64,65 istype 'com'; "RAM Data"
ram_data = [RD7..RD0];
equations


"Data Clock Generation"
"---------------------"

"Here we generate the data clock using a ring oscillator."
"Buffer the ring oscillator output with DCKO to isolate"
"the ring from its loads."
declarations
R1..R8 node istype 'com,keep'; "Ring Oscillator"
equations

"Each gate in the ring oscillator adds two propagation delays"
"to the data clock period. With the LC4256V-10I we find that"
"eight gates gives us a period of 24.4 ns. Each gate contributes"
"roughly 3 ns. With a chip this fast or faster, the largest"
"deviation from 25 ns we will have to accept is 1.5 ns. Our main"
"concern for accuracy in the data clock is serial byte upload"
"to the LWDAQ driver. This upload requires that ten clock cycles"
"take 250+-20 ns. Our ring oscillator can be calibrated to 250"
"+-15 ns."
[R8..R1]=[R7..R1,!R8 & !RESET];
DCKO=R1;


"Reference Clock"
"---------------"

"The reference clock is exactly 30.768 kHz, and we use it for"
"our longer time measurements."

declarations
RCK node istype 'reg,keep'; "Reference Clock"
equations

RCK.clk = DCK;
RCK := ARCK;


"LWDAQ Command and Address Decoding"
"----------------------------------"

"This LWDAQ receiver uses the 40-MHz data clock to generate"
"the DA and DDA signals. We synchronise the incoming serial"
"logic signal, A, with the data clock."

declarations
SA node istype 'reg'; "Synchronized A"
DSA node istype 'reg'; "Delayed SA"
DA node istype 'com,keep'; "Delayed A Rising Edge"
DDA node istype 'com,keep'; "Delayed DA"
AA node istype 'reg'; "Address Active"
DAA node istype 'reg'; "Delayed AA"
CA node istype 'reg'; "Command Active"
DCA node istype 'reg'; "Delayed CA"
ER,Q1..Q16 node istype 'reg'; "Receiver Bits"
LT3..LT0 node istype 'reg'; "LWDAQ Timer"
lt = [LT3..LT0];
AS node istype 'reg'; "Address Strobe"
CS node istype 'reg'; "Command Strobe"
DS node istype 'reg'; "Data Strobe"
DC1..DC16 node istype 'reg';"Device Command Bits"
DA1..DA16 node istype 'reg';"Device Address Bits"
WAKE node istype 'com'; "Wake"
DTX node istype 'com'; "Device Transmit"
equations

"We synchronize A with DCK, and provide a delayed"
"version of A that allows us to detect edges."
[SA,DSA].clk = DCK;
[SA,DSA].aclr = RESET;
SA := A;
DSA := SA;

"This timer allows us to generate the Delayed A (DA)"
"and Double-Delayed A (DDA) signals for serial reception."
lt.clk = DCK;
lt.aclr = RESET;
when lt==0 then {
  when SA & !DSA then lt:=1
  else lt:=0;
} else {
  when lt==9 then lt:=0
  else lt:=lt+1;
}
DA = (lt==4);
DDA = (lt==9);

"We use DCK to clock the receiver registers, and RESET to"
"clear them."
[ER,Q1..Q16,AA,DAA,AS,CA,DCA,CS,DS,DC1..DC16,DA1..DA16].clk = DCK;
[ER,Q1..Q16,AA,DAA,AS,CA,DCA,CS,DS,DC1..DC16,DA1..DA16].aclr = RESET;

"We move bits along the shift register on DA."
when DA then [ER,Q1..Q16] := [SA,ER,Q1..Q15];
else [ER,Q1..Q16] := [ER,Q1..Q16];

"Address Active provides a pulse that begins with DDA"
"on the start bit of an address transmission, and ends"
"with the stop bit of an address transmission. Delayed"
"AA allows us to create Address Strobe, or AS. Address"
"Strobe provides a pulse at the end of an address"
"reception. We clock the receiver bits into the address"
"register on a rusing edge of AS."
when DDA then AA := (!AA & !SA & !ER) # (AA & !SA)
else AA := AA;
DAA := AA;
AS := DAA & !AA;
when AS then [DA1..DA16] := [Q1..Q16]
else [DA1..DA16] := [DA1..DA16];

"Command Active provides a pulse that begins with DDA"
"on the start bit of a command transmission, and ends"
"with the stop bit of a command transmission. Delayed"
"CA allows us to create Command Strobe, or CS. Command"
"strobe provides a pulse at the end of each command"
"reception. We clock the receiver bits into the command"
"register on a rusing edge of CS."
when DDA then CA := (!CA & !SA & ER) # (CA & !SA)
else CA := CA;
DCA := CA;
CS := DCA & !CA;
when CS then [DC1..DC16] := [Q1..Q16]
else [DC1..DC16] := [DC1..DC16];

"Data Strobe identifies a solitary low pulse on A. A"
"solitary low pulse, combined with DTX, indicates that"
"the drivers is expecting this device to upload eight"
"bits of data."
DS := DDA & SA & !AA & !CA;

"WAKE bit."
WAKE = DC8;

"Device Transmit Bit"
DTX = DC5;

"We enable the return LVDS driver when DC7 is set."
LB = DC7;

"We loop back A to the driver so long as DTX is not set."
when !DTX then B = A;


"Data Transmitter"
"----------------"

"The transmitter sends bytes back to the driver. It waits for"
"DS combined with DTX (DC5). When it receives DS and DTX, it"
"waits for Transmission Byte Load (TBL). The transmitter uses"
"DCK to time its serial transmission to the driver. It transmits"
"a leading zero followed by the eight bits of the transmission"
"byte (tb)."

declarations
TS4..TS0 node istype 'reg'; "Transmit State"
TB7..TB0 node istype 'reg'; "Transmission Bits"
ts=[TS4..TS0];"Transmission State"
tb=[TB7..TB0]; "Transmission Byte"
TBL node istype 'reg'; "Transmitter Byte Load"
TBO node istype 'com,keep'; "Transmitter Bit Out"
TBFD1,TBFD0 node istype 'reg'; "TB Fake Data Counter"
tbfd=[TBFD1,TBFD0];
equations

"We assert Transmit Byte Load, TBL, elsewhere in the code"
"when we want to clock ram_data.pin into the Transmit Byte."
TBL.clk = DCK;
TBL.aclr = RESET; 

"The Transmit Byte, tb, holds a byte for transmission to"
"the LWDAQ driver."
tb.clk = DCK;
tb.aclr = RESET;

"The Transmitter State, ts, controls serial transmission"
"to the LWDAQ driver of the Transmi Byte."
ts.clk = DCK;
ts.aclr = RESET;
state_diagram ts;
  state 0:if DS & DTX then 1 else 0;
  state 1:
    if !DC5 then 0;
    if DTX & TBL then 2;
    if DTX & !TBL then 1;
  state 2:goto 3;"Start Bit"
  state 3:goto 4;"Start Bit"
  state 4:goto 5;"TB7"
  state 5:goto 6;"TB7"
  state 6:goto 7;
  state 7:goto 8;
  state 8:goto 9;
  state 9:goto 10;
  state 10:goto 11;
  state 11:goto 12;
  state 12:goto 13;
  state 13:goto 14;
  state 14:goto 15;
  state 15:goto 16;
  state 16:goto 17;
  state 17:goto 18;
  state 18:goto 19;"TB0"
  state 19:goto 20;"TB0"
  state 20:goto 0;"Stop Bit"
equations;

"TBO is the output of the bit transmitter. It passes through"
"the LVDS return and so along the cables to the driver."
TBO = (
    (ts==0)  & 1   "Idle Bit 1"
  # (ts==1)  & 1   "Idle Bit 1"
  # (ts==2)  & 0   
  # (ts==3)  & 0
  # (ts==4)  & TB7
  # (ts==5)  & TB7
  # (ts==6)  & TB6
  # (ts==7)  & TB6
  # (ts==8)  & TB5
  # (ts==9)  & TB5
  # (ts==10) & TB4
  # (ts==11) & TB4
  # (ts==12) & TB3
  # (ts==13) & TB3
  # (ts==14) & TB2
  # (ts==15) & TB2
  # (ts==16) & TB1
  # (ts==17) & TB1
  # (ts==18) & TB0
  # (ts==19) & TB0
  # (ts==20) & 1   "Stop Bit 1"
);

"We return TBO to the driver when DTX is set."
when DTX then B = TBO;

"We load the transmitter byte from the RAM data bus. When"
"some other part of the firmware asserts TBL."
when !fake_data then {
  tb.clk = DCK;
  tb.aclr = RESET;
  when TBL then tb:=ram_data.pin;
  else tb:=tb;
}

"We can generate fake data to check for errors in the"
"upload to the LWDAQ driver, as opposed to errors in"
"RF reception. The Recorder instrument will interpret"
"the fake data as a time stamp."
tbfd.clk=DCK;
tbfd.aclr=RESET;
when fake_data then {
  TBL=1;
  when (ts==20) then tbfd:=tbfd+1
  else tbfd:=tbfd;
  when (tbfd==0) then tb:=^h05;
  when (tbfd==1) then tb:=^hAA;
  when (tbfd==2) then tb:=^hFF;
  when (tbfd==3) then tb:=^d0;
}

"Receiver"
"--------"

declarations
SC node istype 'reg'; "Synchronized C"
DSC node istype 'reg'; "Delayed SC"
RVS4..RVS0 node istype 'reg'; "Receiver State"
rvs=[RVS4..RVS0];
RVD23..RVD0 node istype 'reg'; "Receiver Data"
rvd=[RVD23..RVD0];
EC3..EC0 node istype 'reg'; "Edge Counter"
ec=[EC3..EC0];
BC4..BC0 node istype 'reg'; "Bit Counter"
bc=[BC4..BC0];
STOP node istype 'com,keep'; "Stop Reception"
DONE node istype 'com,keep'; "Done Receiving"
STORED node istype 'com,keep'; "Data Stored in RAM"
MATCH node istype 'com,keep'; "ID Match"
EDGE node istype 'com,keep'; "Edge on C"
TT7..TT0 node istype 'reg'; "Transmission Timer"
tt=[TT7..TT0];
equations

[SC,DSC].clk = DCK;
SC := C;
DSC := SC;
EDGE = (SC & !DSC) # (!SC & DSC);

declarations
rvs_rest = ^d0;
rvs_s1 = 1;
rvs_s2 = 2;
rvs_s3 = 3;
rvs_s4 = 4;
rvs_s5 = 5;

rvs_e1 = 6;
rvs_e2 = 7;
rvs_e3 = 8;
rvs_e4 = 9;
rvs_e5 = 10;

rvs_r2 = 16;
rvs_r3 = 17;
rvs_r4 = 18;
rvs_r5 = 19;

rvs_receive_bit = 21;
rvs_one = 22;
rvs_zero = 23;
rvs_check = 24;
rvs_store = 25;

rvs_clr_ec = 31;
equations

rvs.clk = DCK;
rvs.aclr = RESET;
state_diagram rvs;
  state rvs_rest: "Waiting for a rising edge."
    if SC & EDGE then {
      "When we see one, if we have already counted"
      "a minimum number of qualifying edges"
      "we can attempt to receive a message."
      if (ec == min_startup_edges) then rvs_e1
      "Otherwise, we check to see if this edge is"
      "a qualifying edge."
      else rvs_s1;
    } else rvs_rest;
  state rvs_s1:"Check for EDGE too soon."
    if EDGE then rvs_clr_ec
    else rvs_s2;
  state rvs_s2:"Check for EDGE too soon."
    if EDGE then rvs_clr_ec
    else rvs_s3;
  state rvs_s3:"Wait for EDGE"
    if EDGE then rvs_rest
    else rvs_s4;
  state rvs_s4:"Wait for EDGE"
    if EDGE then rvs_rest
    else rvs_s5;
  state rvs_s5:"Check for EDGE soon enough."
    if EDGE then rvs_rest 
    else rvs_clr_ec;

  state rvs_e1:"Check for EDGE too soon."
    if EDGE then rvs_clr_ec
    else rvs_e2;
  state rvs_e2:"Check for EDGE too soon."
    if EDGE then rvs_clr_ec
    else rvs_e3;
  state rvs_e3:"Check for EDGE"
    if EDGE then rvs_rest
    else rvs_e4;
  state rvs_e4:"Nominal time for edge."
    if EDGE then rvs_rest
    else rvs_e5;
  state rvs_e5:"Check for !EDGE."
    "By now we are certain that the first transition instant"
    "after our rising edge has passed by. If we still have"
    "!EDGE, then we still have SC, which means we can now"
    "expect a start bit. The start bit is a zero, which takes"
    "the form of a falling edge."
    if EDGE then rvs_rest
    else rvs_receive_bit;
 
  state rvs_r2:"Check for EDGE too soon."
    if EDGE then rvs_clr_ec
    else rvs_r3;
  state rvs_r3:goto rvs_r4;
  state rvs_r4:goto rvs_r5;
  state rvs_r5:goto rvs_receive_bit;

  state rvs_receive_bit:
    if STOP then rvs_clr_ec
    else if SC & EDGE then rvs_one
    else if !SC & EDGE then rvs_zero
    else rvs_receive_bit;
  
  state rvs_one:
    if EDGE then rvs_clr_ec
    else if !DONE then rvs_r2
    else rvs_check;
  state rvs_zero:
    if EDGE then rvs_clr_ec
    else if !DONE then rvs_r2
    else rvs_check;

  state rvs_check:
    if MATCH then rvs_store
    else rvs_clr_ec;
  state rvs_store:
    if STORED then rvs_clr_ec
    else rvs_store;

  state rvs_clr_ec:goto rvs_rest;
equations


"The Edge Counter counts the number of startup falling edges"
"before proper reception begins."
ec.clk = DCK;
ec.aclr = RESET;
when (rvs==rvs_s3) then ec:=ec+1
else when (rvs==rvs_clr_ec) then ec:=0
else ec:=ec;

"The Bit Counter counts the number of bits received."
bc.clk = DCK;
bc.aclr = RESET;
when (rvs==rvs_rest) then bc:=0
else when (rvs==rvs_r2) then bc:=bc+1
else bc:=bc;

"We assert DONE when we have received the message bits plus"
"the start bit."
DONE = (bc == num_message_bits);

"The transmission timer starts when we begin waiting for the"
"transmission's first zero bit."
tt.clk = DCK;
tt.aclr = RESET;
when (rvs==0) then tt:=0
else tt:=tt+1;

"We assert STOP when the transmission timer, which is counting"
"DCK cycles, exceeds max_transmission_time."
STOP = (tt>max_transmission_time);

"We shift the incoming bits into the received data register."
rvd.clk = DCK;
rvd.aclr = RESET;
when rvs==rvs_one then [RVD23..RVD0]:=[RVD22..RVD0,1]
else when rvs==rvs_zero then [RVD23..RVD0]:=[RVD22..RVD0,0]
else when rvs==0 then rvd:=0
else rvd:=rvd;

"MATCH indicates that the ID and !ID match in the received data,"
"and that the ID is not zero. We don't accept transmissions with"
"ID zero, because zero is reserved for the timestamp."
MATCH = ([RVD23,RVD22,RVD21,RVD20] == [!RVD3,!RVD2,!RVD1,!RVD0])
	& ([RVD23,RVD22,RVD21,RVD20] != 0);


"Address Counters"
"----------------"

declarations
SA18..SA0 node istype 'reg'; "Data Address"
store_addr = [SA18..SA0];
sab0=[SA7..SA0]; "Store Address byte zero"
sab1=[SA15..SA8]; "Store address byte one"
sab2=[SA18..SA16]; "Store address byte two"
SAC0,SAC1 node istype 'com'; "Data Address Carry"
SAI node istype 'reg'; "Data Address Increment"
TX18..TX0 node istype 'reg'; "Data Address"
transmit_addr = [TX18..TX0];
txb0=[TX7..TX0]; "Transmit address byte zero"
txb1=[TX15..TX8]; "Transmit address byte one"
txb2=[TX18..TX16]; "Transmit address byte two"
TXC0,TXC1 node istype 'com'; "Transmit Address Carry"
TXI node istype 'reg'; "Data Address Increment"
!AE0 node istype 'com,keep'; "Addresses Equal Byte 0"
!AE1 node istype 'com,keep'; "Addresses Equal Byte 1"
!AE2 node istype 'com,keep'; "Addresses Equal Byte 2"
AE node istype 'com'; "Addresses Equal"
equations

"The store address is the RAM address at which we store"
"data."
store_addr.clk = DCK;
store_addr.aclr = RESET;
SAC0 = (sab0==^hFF);
SAC1 = (sab1==^hFF);
SAI.clk = DCK;
when SAI then
{
  sab0 := sab0+1;
  when SAC0 then sab1 := sab1+1;
  else sab1 := sab1;
  when SAC1 & SAC0 then sab2 := sab2+1;
  else sab2 := sab2;
} else {
  store_addr := store_addr;
}

"The transmit address is the RAM address from which"
"we read data to transmit."
transmit_addr.clk = DCK;
transmit_addr.aclr = RESET;
TXC0 = (txb0==^hFF);
TXC1 = (txb1==^hFF);
TXI.clk = DCK;
when TXI then
{
  txb0 := txb0+1;
  when TXC0 then txb1 := txb1+1;
  else txb1 := txb1;
  when TXC1 & TXC0 then txb2 := txb2+1;
  else txb2 := txb2;
} else {
  transmit_addr := transmit_addr;
}

"Address Equal is true when the store address equals the"
"transmit address."
AE0 = (sab0 == txb0);
AE1 = (sab1 == txb1);
AE2 = (sab2 == txb2);
AE = AE0 & AE1 & AE2;


"Time Stamp"
"----------"

declarations
STAMP23..STAMP0 node istype 'reg'; "Time Stamp"
timestamp=[STAMP23..STAMP0];
equations

timestamp.clk = RCK;
timestamp.aclr = RESET;
timestamp := timestamp+1;


"RAM Interface"
"-------------"

declarations
RCS4..RCS0 node istype 'reg'; "Ram Controller State"
rcs=[RCS4..RCS0];
RDOE node istype 'com'; "RAM Data Output Enable (from this chip)"
TSS1..TSS0 node istype 'reg'; "Time Stamp State"
tss=[TSS1..TSS0];
equations

tss.clk = DCK;
tss.aclr = RESET;
state_diagram tss;
  state 0:if [STAMP7..STAMP0]==0 then 1 else 0;
  state 1:if rcs==9 then 2 else 1;
  state 2:if [STAMP7..STAMP0]==0 then 2 else 0;
equations;

rcs.clk = DCK;
rcs.aclr = RESET;
state_diagram rcs;
  state 0:
    if (rvs==rvs_store) then 1 
    else if (tss==1) then 9 
    else if (ts==1) & !AE then 7
    else 0;
  state 1:goto 2;
  state 2:goto 3;
  state 3:goto 4;
  state 4:goto 5;
  state 5:goto 6;
  state 6:goto 17;
  state 7:goto 8;
  state 8:goto 0;
  state 9:goto 10;
  state 10:goto 11;
  state 11:goto 12;
  state 12:goto 13;
  state 13:goto 14;
  state 14:goto 15;
  state 15:goto 16;
  state 16:goto 0;
  state 17:goto 15; "this state lets us assert STORED safely"
equations

"Tell the receiver that we have stored its data."
STORED = (rcs==17);

ram_data.oe = RDOE;
RCE.clk = DCK;

when (rcs==0) then {
  ram_addr = store_addr
  ram_data = 0;
  RW = 1;
  ROE = 0;
  RCE := 0;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
} 
when (rcs==1) then {
  ram_addr = store_addr;
  ram_data = [RVD23..RVD16];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 1;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==2) then {
  ram_addr = store_addr;
  ram_data = [RVD23..RVD16];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==3) then {
  ram_addr = store_addr;
  ram_data = [RVD15..RVD8];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 1;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==4) then {
  ram_addr = store_addr;
  ram_data = [RVD15..RVD8];
  RW = 1;
  ROE = 0;
  RCE := 0;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==5) then {  
  ram_addr = store_addr;
  ram_data = [RVD7..RVD0];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 1;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==6) then {
  ram_addr = store_addr;
  ram_data = [RVD7..RVD0];
  RW = 1;
  ROE = 0;
  RCE := 0;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==7) then {
  ram_addr = transmit_addr;
  ram_data = 0;
  RW = 0;
  ROE = 1;
  RCE := 1;
  SAI := 0;
  TXI := 0;
  TBL := 1;
  RDOE = 0;
}
when (rcs==8) then {
  ram_addr = transmit_addr;
  ram_data = 0;
  RW = 0;
  ROE = 1;
  RCE := 0;
  SAI := 0;
  TXI := 1;
  TBL := 0;
  RDOE = 0;
}
when (rcs==9) then {
  ram_addr = store_addr;
  ram_data = [0,0,0,0,STAMP23..STAMP20];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 1;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==10) then {
  ram_addr = store_addr;
  ram_data = [0,0,0,0,STAMP23..STAMP20];
  RW = 1;
  ROE = 0;
  RCE := 0;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==11) then {
  ram_addr = store_addr;
  ram_data = [STAMP19..STAMP12];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 1;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==12) then {
  ram_addr = store_addr;
  ram_data = [STAMP19..STAMP12];
  RW = 1;
  ROE = 0;
  RCE := 0;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==13) then {
  ram_addr = store_addr;
  ram_data = [STAMP11..STAMP8,1,1,1,1];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 1;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==14) then {
  ram_addr = store_addr;
  ram_data = [STAMP11..STAMP8,1,1,1,1];
  RW = 1;
  ROE = 0;
  RCE := 0;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==15) then {
  ram_addr = store_addr;
  ram_data = [STAMP7..STAMP0];
  RW = 1;
  ROE = 0;
  RCE := 1;
  SAI := 1;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}
when (rcs==16) then {
  ram_addr = store_addr;
  ram_data = [STAMP7..STAMP0];
  RW = 1;
  ROE = 0;
  RCE := 0;
  SAI := 0;
  TXI := 0;
  TBL := 0;
  RDOE = 1;
}

end