"<pre>
module P3025A

title 'P3025A'

"Version 1: Based on P207501A."

"Version 2: [24-JUL-18] Double the length of the pixel intensity read pulses by copying from A2086A05."
"Make clock logic signals behave properly when !WAKE."


declarations

"Constants"
da_delay = 9; "CK periods to DA"
dda_delay = 18; "CK periods to DDA"
run_time = dda_delay+3; "CK periods to run"

"Inputs"
A pin 2; "LVDS Input"
!RST pin 24;"Power-Up Reset"

"Outputs"
LB pin 3 istype 'com'; "Loop Back"			
WAKE pin 14 istype 'com'; "Wake"
TP1,TP2 pin 47,48 istype 'com';
!V1,!V2,!V3 pin 27,31,32 istype 'com'; "Vertical Clocks"
RDP pin 28 istype 'com'; "Read Pulse"
H1,H2 pin 39,38 istype 'com'; "Horizontal Clocks"
S1,S2 pin 23,22 istype 'com'; "Substrate Clocks"
R pin 26 istype 'com'; "Reset Clock"
!CCD1 pin 33 istype 'com';
ON1..ON6 pin 16, 46, 9, 10, 20, 8 istype 'com'; 

"Command Receiver Nodes"
SA node istype 'reg'; "Synchronized A"
DSA node istype 'reg'; "Delayed SA"
DA node istype 'reg'; "Delayed A Rising Edge"
DDA node istype 'reg'; "Delayed DA"
AA node istype 'reg'; "Address Active"
CA node istype 'reg'; "Command Active"
ER,Q1..Q16 node istype 'reg'; "Receiver Bits"
LT4..LT0 node istype 'reg'; "LWDAQ Timer"
lt = [LT4..LT0];
DS node istype 'com'; "Data Strobe"
DC1..DC16 node istype 'reg';"Device Command Bits"
DA0..DA15 node istype 'reg';"Device Address Bits"

"Ring Oscillator Notes"
RO1,RO2 node istype 'com,keep'; "Ring Oscillator"
CK node istype 'reg,keep'; "Clock"
RUN node istype 'reg,keep';
equations 


"Clock Generation"
"----------------"

"The RUN flag controls the ring oscillator. When the ring"
"oscillator runs, it causes lt to increment. When lt reaches"
"a threshold, we clear the RUN flag."
RUN.aclr = (lt == run_time);
RUN := 1;
RUN.clk = A;

"Here we generate our clock with a ring oscillator."
"The ring oscillator consists of two combinatorial gates."
RO1 = RO2;
RO2 = !RO1 & RUN;
CK.clk = RO1;
CK:=!CK;


"Command and Address Decoding"
"----------------------------"

"This LWDAQ receiver uses the 40-MHz data clock to generate"
"the DA and DDA signals. We synchronise the incoming serial"
"logic signal, A, with the data clock."


"We synchronize A with DCK, and provide a delayed"
"version of A that allows us to detect edges."
[SA,DSA].clk = CK;
[SA,DSA].aclr = RST;
SA := A;
DSA := SA;

"This timer allows us to generate the Delayed A (DA)"
"and Double-Delayed A (DDA) signals for serial reception."
lt.clk = CK;
lt.aclr = !RUN;
lt := lt+1;
DA.clk = !CK;
DA.aclr = RST;
DA := (lt==da_delay);
DDA.clk = !CK;
DDA.aclr = RST;
DDA := (lt==dda_delay);

"The command or address bits enter a sixteen-bit shift register."
[ER,Q1..Q16].clk = DA;
[ER,Q1..Q16].aclr = RST;
[ER,Q1..Q16] := [SA,ER,Q1..Q15];

"Address Active, or AA, provides a pulse that begins with DDA"
"on the start bit of an address transmission, and ends with DDA"
"on the stop bit of an address transmission. We clock the receiver"
"bits into the address register on a rising edge of AS."
AA.clk = DDA;
AA := (!AA & !CA & !SA & !ER) # (AA & !SA);
[DA0..DA15].clk = !AA;
[DA0..DA15].aclr = RST;
[DA0..DA15] := [Q1..Q16];

"Command Active, or CA, provides a pulse that begins with DDA"
"on the start bit of a command transmission, and ends with DDA"
"on the stop bit of a command transmission. We clock the receiver"
"bits into the command register on a rising edge of CS."
CA.clk = DDA;
CA := (!AA & !CA & !SA & ER) # (CA & !SA);
[DC1..DC16].clk = !CA;
[DC1..DC16].aclr = RST;
[DC1..DC16] := [Q1..Q16];

"Data Strobe identifies a solitary low pulse on A. A"
"solitary low pulse, combined with DTX, indicates that"
"the drivers is expecting this device to upload eight"
"bits of data."
DS = DDA & SA & !AA & !CA;


"Command Bit Allocation"
"----------------------"

"WAKE bit."
WAKE = DC8;

"We enable the return LVDS driver when DC7 is set."
LB = DC7;

"When the board is awake, we assert the clock values that we receive"
"directly from the driver."
when WAKE then {
  RDP = DC1;
  S1 = DC6;
  S2 = !DC6;
  V3 = DC5;
  V2 = DC4;
  V1 = DC3;
} else {
"When board is asleep, we want all the ccd clock phase outputs to be zero"
"so that we do not drive any current into the level shifting op-amps."
"Phases V1-V3 are negated at the pins, so if we want a LO or 0 value at the"
"pin, we must set these to HI or 1."
  RDP = 0;
  S1 = 0;
  S2 = 0;
  V3 = 1;
  V2 = 1;
  V1 = 1;
}

declarations
H node istype 'com';
HCS0..HCS3 node istype 'reg';
hcs=[HCS3..HCS0];
HRO1,HRO2 node istype 'com,keep';
HCK node istype 'reg';
HRUN node istype 'reg';
equations

"The Horizontal Ring Osicllator provides timing for the horizontal"
"clock of the image sensor. We use the same system we use for the"
"main ring oscillator. Here we start the ring when DC2 is set and
"we see a falling edge on A."
HRUN.aclr = (hcs == 15);
HRUN := 1;
HRUN.clk = !A & DC2;
HRO1 = HRO2;
HRO2 = !HRO1 & HRUN;
HCK.clk = HRO1;
HCK := !HCK;

"The Horizontal Clock state machine provides the timing we need"
"to generate the horizontal clock pulses and reset pulse."
hcs.clk = HCK;
hcs.aclr = !HRUN;
hcs := hcs+1;

"The H bit controls the horizontal clock phases. When DC2 is unasserted, we"
"always assert H, which drives H1 lo and H2 hi. This is the state we are in"
"during vertical transfer. But once DC2 goes hi, in preparation for horizontal"
"transfer, H will be unasserted for a while, until the first negative pulse on"
"SA clocks the first pixel into the output gate."
H = !DC2 
  # (hcs==1) 
  # (hcs==2) 
  # ((hcs==3)&!DC16)
  # ((hcs==4)&!DC16)
  # (hcs==5)
  # (hcs==6)
  # (hcs==7)
  # (hcs==8)
  # (hcs==9)
  # (hcs==10)
  # (hcs==11)
  # (hcs==12);

"When we create the horizontal clock outputs, we make sure they are 0V when"
"the board is alseep. The reset pulse follows the horizontal clock pulse."
when WAKE then {
  H2 = H;
  H1 = !H;
  R = ((hcs==13) # (hcs==14));
} else {
  H2 = 0;
  H1 = 0;
  R = 0;
}


CCD1 = DC9;
ON1 = DC10;
ON2 = DC11;
ON3 = DC12;
ON4 = DC13;
ON5 = DC14;
ON6 = DC15;

"Test Points"
"-----------"

TP1 = DA;
TP2 = DDA;

end