module Decoder

title 'Decoder'


"Version 1: The Message Decoder is duplicated eight times in the Data Receiver A3027"
"firmware. It is almost identical to the Message Receiver in the P3007C07 firmware. It"
"accepts as input a signal Q, which is the output of a comparator at the end of one"
"of the A3027 demodulating amplifiers. The Decoder runs off a 40 MHz clock that must"
"be applied to CK. It resets on RST. It shifts its message data out of M on the rising"
"edge of CK when we assert S. Thus the transfer of the message, which includes a four-"
"bit ID and a sixteen-bit data value, takes place with twenty serial shifts. The"
"serial output takes more time than parallel, but saves gates in the compiled code."

"The Decoder in its rest state is waiting for transitions on Q. It synchronizes Q to"
"its clock and uses a delayed version of Q to detect transitions. If it receives."
"five consecutive rising edges separated by 200+-25 ns, it starts to receive a"
"message. The message consists of rising and falling edges, each edge following the"
"previous edge by 200+-25 ns. A rising edge is a 1, a falling edge is a 0. If the"
"edge does not occur within this time window, the Decoder aborts and returns to its"
"rest state."

"A complete message consists of twenty-four bits. The Decoder checks to see if the"
"first four bits are the complement of the final four bits, as is required by the"
"SCT message protocol. If so, the Decoder sets its RDY output and waits for CNT"
"before it returns to its rest state to await another message. If the first and last"
"four bits are not complimentary, the Decoder discards the corrupted message and"
"returns to its rest state."

"Version 2: We change RDY to a registered node clocked on !CK so that the compiler"
"won't eliminate it later. The node takes one more register, but avoids bringing"
"all five rvs bits into the calculation of MDRDY."

"Version 4: We remove the bit counter and use the edge counter for both the start"
"bits and the message bits. This saves three registers, and in the octal antenna"
"code, we end up with forty fewer outputs. We add the RCV output that we can use"
"to indicate the reception of a message."

declarations

"Inputs"
Q pin; "Demodulator Output"
CNT pin; "Continute"
CK pin; "Clock, 40 MHz"
RST pin; "Reset"
S pin; "Shift"

"Outputs"
RDY pin istype 'reg'; "Message is Ready"
M pin istype 'com'; "Serial Message Bit"
RCV pin istype 'reg'; "Receiving Message"

"Constants that Define Message Structure"
min_sync_edges=5; 
num_message_bits=24;

SQ node istype 'reg'; "Synchronized Q"
DSQ node istype 'reg'; "Delayed SQ"
RVS4..RVS0 node istype 'reg'; "Receiver State"
rvs=[RVS4..RVS0];
RVD23..RVD0 node istype 'reg'; "Receiver Data"
rvd=[RVD23..RVD0];
EC4..EC0 node istype 'reg'; "Edge Counter"
ec=[EC4..EC0];
DONE node istype 'com,keep'; "Done Receiving"
MATCH node istype 'com,keep'; "ID matches !ID"

equations

[SQ,DSQ].clk = CK;
SQ := Q;
DSQ := SQ;

declarations
rvs_rest = ^d0;

rvs_s1 = 1;
rvs_s2 = 2;
rvs_s3 = 3;
rvs_s4 = 4;
rvs_s5 = 5;

rvs_s6 = 6;
rvs_s7 = 7;;
rvs_s8 = 8;
rvs_s9 = 9;
rvs_s10 = 10;

rvs_r2 = 11;
rvs_r3 = 12;
rvs_r4 = 13;
rvs_r5 = 14;
rvs_r6 = 15;

rvs_receive_start = 16;
rvs_receive_1 = 17;
rvs_receive_2 = 18;
rvs_receive_3 = 19;
rvs_receive_4 = 20;

rvs_one = 24;
rvs_zero =25;
rvs_check = 26;
rvs_store = 27;

rvs_clr_ec = 31;
equations

rvs.clk = CK;
rvs.aclr = RST;
state_diagram rvs;
  state rvs_rest: "Waiting for a rising edge."
    if SQ & !DSQ then rvs_s1
    else rvs_rest;
  state rvs_s1: "Check for !SQ too soon"
    if !SQ then rvs_clr_ec
    else rvs_s2;
  state rvs_s2: "Check for !SQ too soon"
    if !SQ then rvs_clr_ec
    else rvs_s3;
  state rvs_s3:"Check for !SQ."
    if !SQ then rvs_s6
    else rvs_s4;
  state rvs_s4:"Check for !SQ."
    if !SQ then rvs_s6
    else rvs_s5;
  state rvs_s5:
    "If SQ, and we have enough edges, this is a start bit."
    if SQ & (ec>=min_sync_edges) then rvs_receive_start
    "If SQ and we don't have enough edges, this is an error,"
    "so clear the edge counter." 
    else if SQ & (ec<min_sync_edges) then rvs_clr_ec
    "We now have !SQ, so check for SQ too soon." 
    else rvs_s6;
  state rvs_s6: "Check for SQ too soon"
    if SQ then rvs_clr_ec
    else rvs_s7;
  state rvs_s7: "Check for SQ too soon"
    if SQ then rvs_clr_ec
    else rvs_s8;
  state rvs_s8: "Check for SQ."
    if SQ then rvs_s1
    else rvs_s9;
  state rvs_s9: "Check for SQ."
    if SQ then rvs_s1
    else rvs_s10;
  state rvs_s10: "Check for SQ."
    if SQ then rvs_s1
    else rvs_clr_ec;

  state rvs_receive_start:
    if SQ & !DSQ then rvs_one
    else if !SQ & DSQ then rvs_zero
    else rvs_receive_2;

  state rvs_r2:
    if (SQ!=DSQ) then rvs_clr_ec
    else rvs_r3;
  state rvs_r3:goto rvs_r4;
  state rvs_r4:goto rvs_r5;
  state rvs_r5:goto rvs_r6;
  state rvs_r6:goto rvs_receive_1;

  state rvs_receive_1:
    if SQ & !DSQ then rvs_one
    else if !SQ & DSQ then rvs_zero
    else rvs_receive_2;
  state rvs_receive_2:
    if SQ & !DSQ then rvs_one
    else if !SQ & DSQ then rvs_zero
    else rvs_receive_3;
  state rvs_receive_3:
    if SQ & !DSQ then rvs_one
    else if !SQ & DSQ then rvs_zero
    else rvs_receive_4;
  state rvs_receive_4:
    if SQ & !DSQ then rvs_one
    else if !SQ & DSQ then rvs_zero
    else rvs_clr_ec;
  
  state rvs_one:
    if !SQ then rvs_clr_ec
    else if !DONE then rvs_r2
    else rvs_check;
  state rvs_zero:
    if SQ then rvs_clr_ec
    else if !DONE then rvs_r2
    else rvs_check;

  state rvs_check:
    if MATCH then rvs_store
    else rvs_clr_ec;
  state rvs_store:
    if CNT then rvs_clr_ec
    else rvs_store;

  state rvs_clr_ec:goto rvs_rest;
equations


"The Edge Counter counts the number of falling edges"
"before proper reception begins, and the number of"
"edge bits after reception starts."
ec.clk = CK;
ec.aclr = RST;
when rvs==rvs_clr_ec then ec:=0
else when (rvs==rvs_s3)&(ec<min_sync_edges) then ec:=ec+1
else when (rvs==rvs_receive_start) then ec:=0
else when (rvs==rvs_r2) then ec:=ec+1
else ec:=ec;

"We assert DONE when we have received the message bits plus"
"the start bit."
DONE = (ec == num_message_bits);

"We shift the incoming bits into the received data register."
rvd.clk = CK;
rvd.aclr = RST;
when rvs==rvs_one then [RVD23..RVD0]:=[RVD22..RVD0,1]
else when rvs==rvs_zero then [RVD23..RVD0]:=[RVD22..RVD0,0]
else when rvs==rvs_rest then rvd:=0
else when (rvs==rvs_store) & S then [RVD23..RVD0]:=[RVD22..RVD0,0]
else rvd:=rvd;

"MATCH indicates that the ID and !ID match in the received data,"
"and that the ID is not zero. We don't accept transmissions with"
"ID zero, because zero is reserved for the timestamp."
MATCH = ([RVD23,RVD22,RVD21,RVD20] == [!RVD3,!RVD2,!RVD1,!RVD0])
	& ([RVD23,RVD22,RVD21,RVD20] != 0);

"We set RDY when we have a message ready to store."
RDY.clk = !CK;
RDY := (rvs == rvs_store);

"The serial output bit is the top bit of the receive data."
M = RVD23;

"The RCV ouput we set when reception starts and reset"
"when we return to the rest state."
RCV.clk = !CK;
when (rvs == rvs_rest) then RCV := 0
else when (rvs == rvs_receive_start) then RCV := 1
else RCV := RCV;

end