"<pre>

MODULE P3049

TITLE 'P3049A'

"Use for A3028KV2 assemblies.

"Version 1 [24-APR-23] Based upon P3028C04.

"Version 2 [26-MAY-23] Revamp version numbers so they make sense.

"Version 3 [08-JUN-23] Fix bug where X is higher channel number, Y is lower.
"Eliminate redundant values of fck_divisor, so that increasing fck_divisor
"always gives longer period."

"Version 4 [05-JUL-23] Fix sample timing bug that generates noise in X and Y
"of dual-channel transmitters. We now select the next channel eck_offset clock
"periods before the end of the sample period. We increase eck_offset as the
"sample period allows.

"Version 5 [19-JUL-23] Increase eck_offset for faster sample rates. Make
"CSS synchronous with TCK and initiate one TCK cycle earlier. Assert CSS 
"for one CK period at end of sample period so as to sample uniformly, thus
"eliminating scatter noise.

declarations


"Configuration Parameters
"========================


"Version | Number | Description
"------------------------------
"   B0      10     single-channel 64 SPS, using X, CR1225
"   B1      11     single-channel 128 SPS, using X, CR1225
"   B2      12     single-channel 256 SPS, using X, CR1225
"   B3      13     single-channel 512 SPS, using X, CR1225
"   B4      14     single-channel 1024 SPS, using X, CR1225
"   B5      15     single-channel 2048 SPS, using X, CR1225
"   E0      10     single-channel 64 SPS, using X, CR2330
"   E1      11     single-channel 128 SPS, using X, CR2330
"   E2      12     single-channel 256 SPS, using X, CR2330
"   E3      13     single-channel 512 SPS, using X, CR2330
"   E4      14     single-channel 1024 SPS, using X, CR2330
"   E5      15     single-channel 2048 SPS, using X, CR2330
"   A0      20     dual-channel 64/64 SPS, common ground, CR1225
"   A1      21     dual-channel 128/128 SPS, common ground, CR1225
"   A2      22     dual-channel 256/256 SPS, common ground, CR1225
"   A3      23     dual-channel 512/512 SPS, common ground, CR1225
"   A4      24     dual-channel 1024/1024 SPS, common ground, CR1225
"   A5      25     dual-channel 2048/2048 SPS, common ground, CR1225
"   H0      20     dual-channel 64/64 SPS, common ground, CR1620
"   H1      21     dual-channel 128/128 SPS, common ground, CR1620
"   H2      22     dual-channel 256/256 SPS, common ground, CR1620
"   H3      23     dual-channel 512/512 SPS, common ground, CR1620
"   H4      24     dual-channel 1024/1024 SPS, common ground, CR1620
"   H5      25     dual-channel 2048/2048 SPS, common ground, CR1620
"   Q0      20     dual-channel 64/64 SPS, common ground, CR2450
"   Q1      21     dual-channel 128/128 SPS, common ground, CR2450
"   Q2      22     dual-channel 256/256 SPS, common ground, CR2450
"   Q3      23     dual-channel 512/512 SPS, common ground, CR2450
"   Q4      24     dual-channel 1024/1024 SPS, common ground, CR2450
"   Q5      25     dual-channel 2048/2048 SPS, common ground, CR2450
"   K0      30     dual-channel 64/32 SPS, separate ground, CR1225
"   K1      31     dual-channel 128/64 SPS, separate ground, CR1225
"   K2      32     dual-channel 256/128 SPS, separate ground, CR1225
"   K3      33     dual-channel 512/256 SPS, separate ground, CR1225
"   K4      34     dual-channel 1024/512 SPS, separate ground, CR1225
"   K5      35     dual-channel 2048/1024 SPS, separate ground, CR1225


"Set the transmitter version number

VERSION = 23;

"The base channel number is the channel number of the first transmit signal
"If only X is enabled, it is the X channel number. If only y is enabled, it
"is the Y channel number. If both are enabled, X is the base number and Y is
"the base number plus one. The base channel number can be 1-14, 17-30, 33-46,
"49-62, 65-78, 81-94, 97-110, 113-126, 129-142, 145-158, 161-174, 177-190,
"193-206, 209-222. These ranges correspond to sets 0-13 respectively,

base_channel_num = 151;

"The base identifier is the channel number modulo sixteen.

base_id = base_channel_num % 16;

"The set number is the channel number divided by sixteen.

set_num = base_channel_num / 16;


"Calibration Parameters
"======================

"Fast Clock Divisor, use to set TCK period in range 195-215 ns. Supported
"range for fck_divisor is 8 to 30.

fck_divisor = 24; 

"Frequency Low, use to center transmit spectrum in range 913-918 MHz.

frequency_low = 24;


"Parameters
"==========

"Version-Dependent Parameters Set Automatically

@IF (VERSION == 10) {
  ck_divisor = 512; "Total Sample Rate 64 SPS
}
@IF (VERSION == 11) # (VERSION == 20) # (VERSION == 30) {
  ck_divisor = 256; "Total Sample Rate 128 SPS
}
@IF (VERSION == 12) # (VERSION == 21) # (VERSION == 31) {
  ck_divisor = 128; "Total Sample Rate 256 SPS
}
@IF (VERSION == 13) # (VERSION == 22) # (VERSION == 32) {
  ck_divisor = 64; "Total Sample Rate 512 SPS
}
@IF (VERSION == 14) # (VERSION == 23) # (VERSION == 33) {
  ck_divisor = 32; "Total Sample Rate 1024 SPS
}
@IF (VERSION == 15) # (VERSION == 24) # (VERSION == 34) {
  ck_divisor = 16; "Total Sample Rate 2048 SPS
}
@IF (VERSION == 25) # (VERSION == 35) {
  ck_divisor = 8; "Total Sample Rate 4096 SPS
}

"Set the transmit clock divisor, tck_divisor, and the ring oscillator length,
"ring_length, to suit fck_divisor. The TCK period will be two gate delays
"multiplied by tck_divisor multiplied by ring_length. For 7.5-ns chips, two
"internal gate delays are roughly 9.3 ns. The ring length must be at least three.
"A ring of two gates runs too fast, causing the counter to skip values. The maximum 
"ring length in this code is 13, but ultimately is limited by the available logic 
"outputs. The tck_divisor must be two or greater. We need at least two divider 
"states to create a symmetric transmit clock signal. And tck_divisor must also be 
"at most thirty-two because we have at most five divisor bits in this
"code.

@IF (fck_divisor == 8)  {tck_divisor = 2; ring_length = 4;}
@IF (fck_divisor == 9)  {tck_divisor = 3; ring_length = 3;}
@IF (fck_divisor == 10) {tck_divisor = 2; ring_length = 5;}
@IF (fck_divisor == 11) {tck_divisor = 4; ring_length = 3;}
@IF (fck_divisor == 12) {tck_divisor = 4; ring_length = 3;}
@IF (fck_divisor == 13) {tck_divisor = 2; ring_length = 7;}
@IF (fck_divisor == 14) {tck_divisor = 5; ring_length = 3;}
@IF (fck_divisor == 15) {tck_divisor = 4; ring_length = 4;}
@IF (fck_divisor == 16) {tck_divisor = 6; ring_length = 3;}
@IF (fck_divisor == 17) {tck_divisor = 5; ring_length = 4;}
@IF (fck_divisor == 18) {tck_divisor = 7; ring_length = 3;}
@IF (fck_divisor == 19) {tck_divisor = 2; ring_length = 11;}
@IF (fck_divisor == 20) {tck_divisor = 8; ring_length = 3;}
@IF (fck_divisor == 21) {tck_divisor = 5; ring_length = 5;}
@IF (fck_divisor == 22) {tck_divisor = 2; ring_length = 13;}
@IF (fck_divisor == 23) {tck_divisor = 9; ring_length = 3;}
@IF (fck_divisor == 24) {tck_divisor = 7; ring_length = 4;}
@IF (fck_divisor == 25) {tck_divisor = 6; ring_length = 5;}
@IF (fck_divisor == 26) {tck_divisor = 8; ring_length = 4;}
@IF (fck_divisor == 27) {tck_divisor = 11; ring_length = 3;}
@IF (fck_divisor == 28) {tck_divisor = 7; ring_length = 5;}
@IF (fck_divisor == 29) {tck_divisor = 9; ring_length = 4;}
@IF (fck_divisor == 30) {tck_divisor = 3; ring_length = 13;}
@IF (fck_divisor == 31) {tck_divisor = 8; ring_length = 5;}
@IF (fck_divisor == 32) {tck_divisor = 7; ring_length = 6;}


frequency_step=2; "HI frequency - LO frequency
enable_rf=1; "Turns on RF oscillator during transmission
I3..I0 node istype 'com'; "Transmitter ID nodes
id = [I3..I0];
CC3..CC0 node istype 'com'; "Completion Code Bits
cc =[CC3..CC0];


"Inputs and Outputs
"==================

CK pin K9; "Clock From 32-kHz Oscillator
F4..F0 pin A1,A3,A4,A6,A7 istype 'reg'; "DAC for frequency
!SHDN pin A2 istype 'com'; "Shutdown Control for Transmitter
TP1 pin F1 istype 'com'; "Test Point 1
TP2 pin G1 istype 'com'; "Test Point 2
TP3 pin H1 istype 'com'; "Test Point 3
!CSS pin K4 istype 'com'; "Chip Select for ADC
SDO pin K5; "Serial Data Out for ADC
SCK pin K7 istype 'com'; "Serial Clock for ADC
SEL pin E10 istype 'reg,pos'; "Serial Data In for ADC
L0..L1 pin C10,B10; "Layout Pins
KP pin D8 istype 'com';


"Nodes
"=====

FCK node istype 'com,keep'; "Fast Clock
TCK node istype 'reg,keep'; "Transmission Clock
ECK node istype 'reg,keep'; "End Clock
VCK node istype 'reg,keep'; "VCO Clock
ST0..ST8 node istype 'reg'; "Sample Timer
SCNT0..SCNT8 node istype 'reg'; "Sample Counter
R1..R12 node istype 'com,keep'; "Ring Oscillator Bit
TXS0..TXS5 node istype 'reg,pos'; "Transmitter State
ACTIVE node istype 'reg,keep'; "Reading and transmitting sample
TXD node istype 'com,keep'; "Transmitter Done
TCKD0..TCKD4 node istype 'reg'; "Transmit Clock Divider
TCKDZ node istype 'reg,keep'; "Transmit Clock Divider Zero
ADC0..ADC3 node istype 'reg'; "ADC Bits
TTS0..TTS3 node istype 'reg'; "Transmit Time Shift
SDOS node istype 'reg,keep'; "SDO Synchronized
XCONV node istype 'com'; "Convert Channel X
TXEN node istype 'com'; "Transmit Enable
BIT node istype 'com,keep'; "The output bit value
RDS node istype 'reg,keep'; "Read Sample


"Sets
"====

"Sample Timer, depends upon ck_divisor to eliminate unused bits.
"Likewise, the active time, which is the moment during the period
"at which we transmit a sample, depends upon how many bits we have
"in the Sample Timer.
@IF (ck_divisor == 8) {
  "Frequency 4096 SPS, scatter is 0-3 ticks.
  st = [ST2..ST0];
  active_time = [0,TTS1,TTS0];
  eck_offset = 3;
}
@IF (ck_divisor == 16) {
  "Frequency 2048 SPS, scatter is 0-7 ticks.
  st = [ST3..ST0];
  active_time = [0,TTS2,TTS1,TTS0];
  eck_offset = 7;
}
@IF (ck_divisor == 32) {
  "Frequency 1024 SPS, scatter is 0-15 ticks.
  st = [ST4..ST0];
  active_time = [0,TTS3,TTS2,TTS1,TTS0];
  eck_offset = 15;
}
@IF (ck_divisor == 64) {
  "Frequency 512 SPS, scatter is 0-15 ticks.
  st = [ST5..ST0];
  active_time = [0,0,TTS3,TTS2,TTS1,TTS0];
  eck_offset = 15;
}
@IF (ck_divisor == 128) {
  "Frequency 256 SPS, scatter is 0-15 ticks.
  st = [ST6..ST0];
  active_time = [0,0,0,TTS3,TTS2,TTS1,TTS0];
  eck_offset = 15;
}
@IF (ck_divisor == 256) {
  "Frequency 128 SPS, scatter is 0-15 ticks.
  st = [ST7..ST0];
  active_time = [0,0,0,0,TTS3,TTS2,TTS1,TTS0];
  eck_offset = 15;
}
@IF (ck_divisor == 512) {
  "Frequency 64 SPS, scatter is 0-15 ticks.
  st = [ST8..ST0];
  active_time = [0,0,0,0,0,TTS3,TTS2,TTS1,TTS0];
  eck_offset = 15;
}


"Transmit Clock Divider, depends upon tck_divisor to eliminate unused
"bits

@IF (tck_divisor <= 4) {
  tckd = [TCKD1..TCKD0];
}
@IF (tck_divisor >= 5) & (tck_divisor <= 8) {
  tckd = [TCKD2..TCKD0];
}
@IF (tck_divisor >= 9) & (tck_divisor <= 16) {
  tckd = [TCKD3..TCKD0];
}
@IF (tck_divisor >= 17) {
  tckd = [TCKD4..TCKD0];
}

txs = [TXS5..TXS0]; "Transmitter State
adc_bits = [ADC3..ADC0]; "ADC Bits
transmit_time_shift = [TTS3..TTS0]; "Transmit Time Shift
frequency = [F4..F0]; "Frequency Voltage for Five-Bit DAC
scnt =[SCNT3..SCNT0];


"Constants
"=========

num_sync_bits=11; "Number of synchronizing bits at transmission start.
num_id_bits = 4; "Number of ID bits
num_start_bits = 1; "Transmitted zero to mark data start
num_stop_bits = 2; "Not transmitted, for txs termination
num_data_bits = 16; "Number of ADC data bits
num_xmit_bits = "Number of transmission bit periods
    num_sync_bits
  + num_start_bits
  + num_id_bits
  + num_data_bits
  + num_id_bits; 
txs_done = "Final state of txs machine
    num_xmit_bits
  + num_stop_bits; 
first_sync_bit = 1;
first_start_bit = first_sync_bit + num_sync_bits;
first_id_bit = first_start_bit + num_start_bits;
first_data_bit = first_id_bit + num_id_bits;
first_cc_bit = first_data_bit + num_data_bits;
start_sck = "The txs state for first SCK falling edge
    first_data_bit - 1;
end_sck = "The txs state for last SCK falling edge
    start_sck + num_data_bits - 1;

equations


"Sample Timing
"=============

"The Sample Timer runs off the 32.678-kHz clock and counts up to
"ck_divisor-1 to give a sample period of 32.768 kHz divided
"by ck_divisor.

st.clk=CK;
when (st==ck_divisor-1) then {
  st:=0;
} else {
  st:=st+1;
}

"The ECK clock occurs at the end of each sample period.

ECK.clk=CK;
ECK:=(st==ck_divisor-eck_offset-1);

"When ACTIVE is asserted, we begin a burst transmission.
"When it is unasserted, we reset the burst transmission
"state machine. We must make sure that ACTIVE remains true
"for long enough for the burst transmission to complete.
"ACTIVE becomes true when the Sample Timer reaches the active
"time set at the end of the previous sample period. This
"active time is made up of the lower four bits of the sample
"transmitted in the previous sample period. Because these
"four bits are dominated by noise, they are random and so
"produce a random disturbance of the transmit instant, which
"avoids systematic collisions between transmitters.

ACTIVE.clk=CK;
ACTIVE:=(st==active_time);

"TXD is true when the transmitter completes its burst
"transmission.

TXD=(txs==txs_done);


"Sample Selection
"================

"The Sample Counter counts sample periods and allows us to decide
"which input to digitize and which channel number to apply to each
"sample transmission. We increment the counter at the end of each
"sample period.

scnt.clk=ECK;
scnt:=scnt+1;


"Select one of the analog signals. For each value of scnt we
"set the id equal to the input selected on the previous value
"of scnt, since the ADC converts at the end of the readout.

@IF (VERSION / 10 == 1) {
  declarations x_id = base_id; y_id = 0; equations
  when scnt == 0  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 1  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 2  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 3  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 4  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 5  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 6  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 7  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 8  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 9  then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 10 then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 11 then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 12 then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 13 then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 14 then {id = x_id; XCONV = 1; TXEN = 1;}
  when scnt == 15 then {id = x_id; XCONV = 1; TXEN = 1;}
} 
@IF (VERSION / 10 == 2) {
  declarations x_id = base_id; y_id = base_id + 1; equations
  when scnt == 0  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 1  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 2  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 3  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 4  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 5  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 6  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 7  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 8  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 9  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 10 then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 11 then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 12 then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 13 then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 14 then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 15 then {id = x_id; XCONV = 0; TXEN = 1;}
}
@IF (VERSION / 10 == 3) {
  declarations x_id = base_id; y_id = base_id + 1; equations
  when scnt == 0  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 1  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 2  then {id = y_id; XCONV = 1; TXEN = 0;}
  when scnt == 3  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 4  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 5  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 6  then {id = y_id; XCONV = 1; TXEN = 0;}
  when scnt == 7  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 8  then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 9  then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 10 then {id = y_id; XCONV = 1; TXEN = 0;}
  when scnt == 11 then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 12 then {id = y_id; XCONV = 1; TXEN = 1;}
  when scnt == 13 then {id = x_id; XCONV = 0; TXEN = 1;}
  when scnt == 14 then {id = y_id; XCONV = 1; TXEN = 0;}
  when scnt == 15 then {id = x_id; XCONV = 0; TXEN = 1;}
}

"Calculate the completion code.

cc = 15 - id + set_num;


"Transmit Clock
"=============

"The ring oscillator turns on when ACTIVE and remains
"on until TXD. Each gate in the ring adds 2 ns to the
"delay around the ring. The period of the oscillation is
"4 ns multiplied by the number of gates.

@IF (ring_length == 2) {
  [FCK,R1]=[R1,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 3) {
  [FCK,R1..R2]=[R1..R2,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 4) {
  [FCK,R1..R3]=[R1..R3,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 5) {
  [FCK,R1..R4]=[R1..R4,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 6) {
  [FCK,R1..R5]=[R1..R5,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 7) {
  [FCK,R1..R6]=[R1..R6,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 8) {
  [FCK,R1..R7]=[R1..R7,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 9) {
  [FCK,R1..R8]=[R1..R8,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 10) {
  [FCK,R1..R9]=[R1..R9,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 11) {
  [FCK,R1..R10]=[R1..R10,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 12) {
  [FCK,R1..R11]=[R1..R11,!FCK & ACTIVE & !TXD];
}
@IF (ring_length == 13) {
  [FCK,R1..R12]=[R1..R12,!FCK & ACTIVE & !TXD];
}

"The transmit clock divider runs off FCK and divides FCK down
"to 5 MHz by correct choice of fck_divisor during transmitter
"calibration. We compute two constants from fck_divisor. One
"is tck_divisor, which sets the transmit clock period as a
"multiple of the fast clock period. The other is ring_length,
"which sets the number of gates in the ring oscillator that
"generates the fast clock. We enable the transmit clock divider
"only when the transmitter is active.

tckd.aclr=!ACTIVE;
tckd.clk=FCK;
when (tckd==tck_divisor-1) then {
  tckd:=0;
} else {
  tckd:=tckd+1;
}

"We detect the transmit clock divider being zero with TCKDZ. We
"clear TCKDZ to zero when the transmitter is inactive.

TCKDZ.aclr=!ACTIVE;
TCKDZ.clk=FCK;
TCKDZ:=(tckd==0);

"The transmit clock should be close to or a little less than 5 MHz,
"with a duty cycle of exactly 50%. Each time the transmit clock counts
"down to zero, we invert the transmit clock.

TCK.aclr=!ACTIVE;
TCK.clk=TCKDZ;
TCK:=!TCK;


"Transmission Control
"====================

"The transmitter state machine steps through all its
"states when ACTIVE is asserted, and then stops in its
"final state, waiting for !ACTIVE, which will reset the
"transmitter state to zero.

txs.aclr=!ACTIVE;
txs.clk=TCK;
when (txs==txs_done) then txs:=txs
else txs:=txs+1;

"Transmit sixteen ADC bits.

when (txs>0) & (txs<num_xmit_bits+1) then {
  when (
      (txs==0)&(1) "shutdown bit
    # (txs>=1)&(txs<first_start_bit) "sync bits
    # (txs==first_id_bit+0)&(I3) "id bit 3
    # (txs==first_id_bit+1)&(I2) "id bit 2
    # (txs==first_id_bit+2)&(I1) "id bit 1
    # (txs==first_id_bit+3)&(I0) "id bit 0
    # (txs>=first_data_bit)&(txs<first_cc_bit)&(SDOS) "ADC bits 15 down to 0
    # (txs==first_cc_bit+0)&(CC3) "cc bit 3
    # (txs==first_cc_bit+1)&(CC2) "cc bit 2
    # (txs==first_cc_bit+2)&(CC1) "cc bit 1
    # (txs==first_cc_bit+3)&(CC0) "cc bit 0
     ) then {BIT = 1} "transmit a 1
    else {BIT = 0} "transmit a 0
} else {BIT = 0} 

"We clock frequency with VCK, which we set up to give the
"bit value calculation time to settle after the rising edge
"of TCK. The VCK clock provides two pulses during each TCK
"period.

VCK.aclr=!ACTIVE;
VCK.clk=FCK;
VCK:=(tckd==1);

"The frequency DAC output is set by FHI and ACTIVE. When ACTIVE is not
"asserted, we set the DAC output to zero so as to stop current flowing
"into the DAC resistors.

frequency.aclr=!ACTIVE;
frequency.clk=VCK;
when TCK $ BIT then frequency := frequency_low + frequency_step
else frequency := frequency_low;

"The adc_bits register has different functions in a reference and analog
"transmitter, but the same clock.

adc_bits.clk=TCK;

"We record the lower ADC bits so they may be used to set
"transmit_time_shift. Transmit Time Shift dictates the next
"ACTIVE period by its inclusion in active_time.

when (txs==end_sck-3) then ADC3:=SDOS else ADC3:=ADC3;
when (txs==end_sck-2) then ADC2:=SDOS else ADC2:=ADC2;
when (txs==end_sck-1) then ADC1:=SDOS else ADC1:=ADC1;
when (txs==end_sck-0) then ADC0:=SDOS else ADC0:=ADC0;

"The transmit time shift value we update at the end of each sample
"period using ECK. We will use however many time shift bits we need
"to produce scatter_xmit.

transmit_time_shift.clk=ECK;
transmit_time_shift:=[ADC3,ADC2,ADC1,ADC0];

"SHDN turns off the RF transmitter

when enable_rf then {
  SHDN=(txs==0) # TXD # !TXEN;
} else {
  SHDN=1;
}

"Conversion Control
"==================

"The !CSS input to the ADC provokes conversion on its rising edge
"and must be low during readout. We have one uniformly-spaced
"pulse of length CK on CSS at the beginning of each sample period,
"followed by another shorter pulse during the ACTIVE CK period.
"If the ACTIVE period occurs at the start of the sample period, we
"have only one short pulse. The short pulse is the readout pulse,
"which also causes a conversion. Most of the time we are converting
"twice during each sample period.

RDS.clk = TCK;
RDS := (txs>=start_sck-2) & (txs<=end_sck+1);
CSS = (st == ck_divisor-1) # RDS;

"We synchronize SDO with TCK.

SDOS.clk = TCK;
SDOS := SDO;

"We clock the ADC bits out of the chip as we transmit
"them, so we have no need for a register in which
"to save them.

SCK = (txs>=start_sck) & (txs<=end_sck) & !TCK;

"We select the signal that will be digitized at the next 
"rising edge of CONV. With SEL = 1, the next sample from 
"the ADC will be of X, otherwise it will of Y. We change
"the state of the switch one CK period after the end of
"the active interval.

SEL.clk = ECK;
SEL := XCONV;


"Test Points
"===========

"The following test points allow us to calibrate the Transmit
"Clock (TCK), check the oscillator (CK), and measure the exact
"sample rate (st=0 pulse).

TP1 = (frequency==frequency_low+frequency_step);
TP2 = CK;
TP3 = (st==0);

"Keeper Outputs
"==============

"We assign TP2 to be a function of the chip pins whose pads
"we use to route signals and power to the center of our ball
"grid array logic chip. Otherwise, these balls are treated by the
"compiler as unconnected, and are assigned pull-up resistors
"that consume current without us having any option to change
"their inputs to HOLD. By declaring each signal, we can set
"their inputs to HOLD in the Constraint Editor.

KP=[L1..L0] != 0;

END