LWDAQ Function Generator (A3050)

© 2024 Nathan Sayer, Open Source Instruments Inc.


Contents

Description
Versions
Design
Operation
Development

Description

In an attempt to automate part of the QC2 procedure for SCTs, we begin the design of a function generator that can be controlled through an RJ-45 socket with LWDAQ. We begin by looking at the design done by Michael Bradshaw (A3031). With our new design, we plan to use a similar method to change frequency output but allow the device to be controllable over a socket without a LWDAQ driver involved. This instrument will allow us to perform a frequency sweep on our circuits and measure the response in a LWDAQ instrument. We begin with the same RCM6700 module and logic as the ALT baseboards. This will provide communication over the socket. The logic will then transmit a signal through two identical channels, starting with an 8-bit DAC. This will output a rough sinusoid that can then be smoothed out with an RC circuit. We switch to different RC circuits depending on the update rate of the signal using DG411Y chips. We include power LEDs and indicator lights to make testing the board easier.

Versions

The first version of the PCB did not route the feedback of the op-amps correctly, and as a result the op-amps consumed too much current. We also forgot to include a programming extension for the logic chip and as a result we had to solder some wires to individual pins. We also plan to replace the 80MHz clock currently on the board with one that has a bigger footprint. The board has plenty of space and it will be easier to solder and test.

Design

S3050A_1: A305001A Schematic
A305001A: A305001A Gerber Files
A305001B: A305001B Gerber Files
S3050D_1: A305001D Schematic
S3050DC: A305002A Schematic
Firmware Repository: Firmware Repository

Operation

Control Space Address (Hex)Contents
00Hardware identifier
12Hardware version
13Software version
18Data address 1
19Data address 2
1AData address 3
1BData address 4
3FData portal
Table: Function Generator Controller Space Adress Map.


Data Address (Hex)Contents
0000...1FFFSample values, Channel 1
4000...5FFFSample values, Channel 2
8000RC filter switch controller, Channel 1
8001RC filter switch controller, Channel 2
8002Divisor, Channel 1, Byte 3
8003Divisor, Channel 1, Byte 2
8004Divisor, Channel 1, Byte 1
8005Divisor, Channel 1, Byte 0
8006Divisor, Channel 2, Byte 3
8007Divisor, Channel 2, Byte 2
8008Divisor, Channel 2, Byte 1
8009Divisor, Channel 2, Byte 0
800AWaveform length, Channel 1, Byte 1
800BWaveform length, Channel 1, Byte 0
800CWaveform length, Channel 2 Byte 1
800DWaveform length, Channel 2 Byte 0
Table: Function Generator Data Adress Space Map.


BinaryHexDecimalResistanceCapacitanceTime Constant
00000001010151 Ω250 pF (parasitic)12.5 ns
00010001111751 Ω1 nF51 ns
00100001213351 Ω7.8 nF398 ns
01000001416551 Ω57 nF3.04 μs
100000018112951 Ω447 nF23.3 μs
000100101218390 Ω1 nF390 ns
001000102234390 Ω7.8 nF3.04 μs
010000104266390 Ω57 nF23.3 μs
1000001082130390 Ω447 nF171 μs
0001010014203 kΩ1 nF3.04 μs
0010010024363 kΩ7.8 nF23.3 μs
0100010044683 kΩ57 nF171 μs
10000100841323 kΩ447 nF1.34 ms
00011000182422 kΩ1 nF23.3 μs
00101000284022 kΩ7.8 nF171 μs
01001000487222 kΩ57 nF1.34 ms
100010008813622 kΩ447 nF9.8 ms
Table: RC filter byte values.


ParameterReset Value (Dec)
Sample Values, Channel 1128 (Output = 0V)
Sample Values, Channel 2128 (Output = 0V)
RC filter switch controller, Channel 11
RC filter switch controller, Channel 21
Divisor, Channel 1, Bytes 0-3All 0
Divisor, Channel 2, Bytes 0-3All 0
Waveform Length, Channel 1, Bytes 0-1All 0
Waveform Length, Channel 2, Bytes 0-1All 0
Table: Reset values for programmable parameters.

The two data address locations that control the RC filters for both channels use 1 byte to control all 8 switches within one channel. The diagram below shows us an example of all the switches being open with the exception of 100 Ω. For more info on how LWDAQ messages are used to communicate with the control space, see LWDAQ Specification. For an example of using control space to create a data space through a data portal, see LWDAQ Driver Manual.



Figure 1: Configuration for RC filter switches.

The waveform generated has a maximum amplitude of +/- 10V but if the channel is terminated with 50 ohms then the maximum amplitude of the waveform becomes +/- 5V. This function generator is designed to provide proper transmission down a 50-ohm coaxial cable terminated with a 50-ohm resistor. We can calculate the frequency of the waveform output as well as its sample frequency using the equations below:


Figure 2: Functions for determining the frequency of the output waveform and its sample frequency

We use some variables to make the equations look neat. We define "waveform frequency" as the frequency of the sine wave, square wave, or arbitrary waveform that is generated on the output of the function generator. We define "sample frequency" as the rate at which the function generator reads from the RAM, moving onto the next sample value. We define "waveform length" as a unitless variable equal to the number of samples required to complete one cycle of the output waveform. Lastly, we define "clock divisor" as the value we provide in order to change the sample rate. We provide a plot of output voltage versus DAC value below such that anyone operating the function generator can generate any voltage within the acceptable range.


Figure 3: Plot of output voltage vs. DAC values

As an example, we will generate a 1.25MHz sine wave. We begin by writing the values [128, 152, 176, 198, 218, 234, 245, 253, 255, 253, 245, 234, 218, 198, 176, 152, 128, 103, 79, 57, 37, 21, 10, 2, 0, 2, 10, 21, 37, 57, 79, 103 (dec)] to the first 32 locations in the data space. Next, we write [1 (dec)] to address 8000 to adjust the RC filters to allow for current to flow through the 100R resistor with no base load capacitor. Lastly, we write [0, 31 (dec)] to address 800A. This changes the waveform length to allow for the first 32 DAC values to be read out repeatedly. Notice that writing 31 as the waveform length allows for a waveform of 32 samples. The actual waveform length will be one more than the value written to the register. We do not change the divisor because we wish to generate 1.25MHz which is achieved with no divisor and a waveform length of 31. The resulting waveform is below:


Figure 4: Sine wave, waveform length= 32, RC= 1, divisor= 0.

Next, we will generate a 100kHz square wave with an offset. We begin by writing [128, 255 (dec)] to the first two locations in the data space. The full range of DAC values is 0 to 255 (dec) so if we change between 128 and 255 the waveform will be offset by 5V and have a ptp amplitude of 10V. We then set the waveform length to 2 by writing [0, 1 (dec)] to 800A. Lastly, we write [0, 0, 0, 199 (dec)] to location 8002. We use the same RC filter as the previous waveform because we want a sharp square wave. The resulting waveform is below:


Figure 5: Square wave, offset= 5V, waveform length= 2, RC= 1, divisor= 199.

Finally, we will generate a smoothed 10kHz sine wave. The 1.25 MHz sine wave was fast enough that it didn't require a base load capacitor to smooth out. Something slower will have noticeable steps if not smoothed. We begin by writing the same DAC sine wave values as the first waveform [128, 152, 176, 198, 218, 234, 245, 253, 255, 253, 245, 234, 218, 198, 176, 152, 128, 103, 79, 57, 37, 21, 10, 2, 0, 2, 10, 21, 37, 57, 79, 103 (dec)] to the first 32 locations in the data space. We then write [0, 31 (dec)] to address 800A to guarentee the waveform reads all 32 DAC values and only those 32 DAC values. We also write [0, 0, 0, 124 (dec)] to location 8002 in order to change the waveform's frequency by a factor of 125. If we write [1 (dec)] to address 8000 then the output will look something like this:


Figure 6: Sine wave, waveform length= 32, RC= 1, divisor= 124.

Notice how we can see each sample as a step rigidly separated from the others. To avoid this, we can write [34 (dec)] to location 8000 which gives us a 10us RC filter. The resulting waveform has about 13% less amplitude but looks much smoother:


Figure 7: Sine wave, waveform length= 32, RC= 34, divisor= 124.

Development

[20-OCT-23] Create manual page.

[25-OCT-23] We receive new PCBs (A305001B) and assemble one. We notice that as soon as power is supplied, the +/-12V DC-DC converter begins buzzing. The logic chip can program so we now have a working extension, but we found that we must remove the feedback capacitors (10pf) on each op-amp in order to avoid drawing too much current. After removing these capacitors, we put a 3.3V 32.768kHz signal through both DAC channels and watch it propagate through the amplifiers. Each channel outputs a 10Vptp 32.768kHz signal with a 0V average.


Figure 5: Input (square) and output (shaped) of the A3050 LWDAQ function generator using a 32.678kHz clock signal.

[18-DEC-23] We program the controller (LCMXO2-7000HC) with a relay interface that maps various address spaces to variables needed to output a function. The data portal is located in the highest location in the control space.

[24-JAN-24] To avoid supply shortage issues later on, we develop a DC-DC converter using the LT8306 no-opto isolated flyback converter. Using the LT8306 datasheet, we come to the following design:


Figure 6: Schematic for PoE to 24V DC-DC converter.

Once assembled, we test the converter by slowly ramping up its input voltage with a DC benchtop power supply and measuring its current consumption as well as its output voltage.


Figure 7: Current Consumption and Output Voltage vs. Input Voltage with a 200 Ohm load.

We then use these measured values to calculate the input power and output power. The effieciency measured in the graph below is defined as the output power divided by the input power.


Figure 8: Efficiency vs. Input Voltage with a 200 Ohm load.

[29-JAN-24] We notice that with a 0.01 Ohm sense resistor the output voltage varies greatly based on input voltage. We increase the sense resistor to 0.025 Ohms and notice that the output voltage stabalizes with respect to input voltage.